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ISL6700
Data Sheet December 29, 2004 FN9077.6
80V/1.25A Peak, Medium Frequency, Low Cost, Half-Bridge Driver
The ISL6700 is an 80V/1.25A peak, medium frequency, low cost, half-bridge driver IC available in 8-lead SOIC and 12-lead QFN plastic packages. The low-side and high-side gate drivers are independently controlled and matched to 25ns. This gives the user maximum flexibility in dead-time selection and driver protocol. Undervoltage protection on both the low-side and high-side supplies force the outputs low. Non-latching, level-shift translation is used to control the upper drive circuit. Unlike some competitors, the high-side output returns to its correct state after a momentary undervoltage of the high-side supply.
Features
* Drives 2 N-Channel MOSFETs in Half-Bridge Configuration * Space Saving SO8 and Low RC-S QFN Packages * Phase Supply Max Voltage to 80VDC * Bootstrap Supply Max Voltage to 96VDC * Drives 1000pF Load with Rise and Fall Times Typ. 15ns * TTL/CMOS Compatible Input Thresholds * Independent Inputs for Non-Half-Bridge Topologies * No Start-Up Problems * Low Power Consumption * Wide Supply Range
Ordering Information
PART NUMBER ISL6700IB ISL6700IBZ (See Note) ISL6700IR ISL6700IRZ (See Note) TEMP. RANGE (C) -40 to 125 -40 to 125 -40 to 125 -40 to 125 PACKAGE 8 Ld SOIC 8 Ld SOIC (Pb-free) 12 Ld 4x4 QFN 12 Ld 4x4 QFN (Pb-free) PKG. DWG. # M8.15 M8.15 L12.4x4 L12.4x4
* Supply Undervoltage Protection * QFN Package - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline * Pb-Free Available (RoHS Compliant)
Applications
* Telecom/Datacom Power Supplies * Half-Bridge Converters * Two-Switch Forward Converters * Active Clamp Forward Converters
Add "-T" suffix to part number for tape and reel packaging. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pinouts
ISL6700IB (SOIC) TOP VIEW
VDD HI LI VSS 1 2 3 4 8 7 6 5 HB HO HS LO HI NC LI 1 2 3 4 VSS 5 NC 6 LO EPAD
ISL6700IR (QFN) TOP VIEW
VDD NC 11 HB 10 9 HO 8 NC 7 HS
12
NOTE: EPAD = Exposed PAD.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2002-2004. All Rights Reserved. All other trademarks mentioned are the property of their respective owners.
ISL6700 Application Block Diagram
+12V +48V
VDD
HB
SECONDARY CIRCUIT
HI CONTROL PWM CONTROLLER LI
DRIVE HI
HO HS
DRIVE LO
LO
ISL6700 VSS
REFERENCE AND ISOLATION
Functional Block Diagram
HB U/V LEVEL SHIFT HO HS
HI
LI
TURN-ON DELAY DETECTOR UNDERVOLTAGE
LO
VDD
VSS EPAD (QFN PACKAGE ONLY)
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FN9077.6 December 29, 2004
ISL6700
+48V +12V
PWM
ISL6700
SECONDARY CIRCUIT
ISOLATION
FIGURE 1. TWO-SWITCH FORWARD CONVERTER
+48V +12V SECONDARY CIRCUIT
PWM
ISL6700
ISOLATION
FIGURE 2. FORWARD CONVERTER WITH AN ACTIVE CLAMP
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FN9077.6 December 29, 2004
ISL6700
Absolute Maximum Ratings
Supply Voltage, VDD (Note 1) . . . . . . . . . . . . . . . . . . . -0.3V to 16V LI and HI Voltages (Note 1) . . . . . . . . . . . . . . . . -0.3V to VDD +0.3V Voltage on HS (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 80V Voltage on HB (Note 1) . . . . . . . . . . . . . . . . VHS-0.3V to VHS+VDD Voltage on LO (Note 1) . . . . . . . . . . . . . . . . . VSS-0.3 to VDD+0.3V Voltage on HO (Note 1) . . . . . . . . . . . . . . . . VHS-0.3V to VHB+0.3V Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns
Thermal Information
Thermal Resistance (Typical) JA (C/W) JC (C/W) SOIC (Note 3) . . . . . . . . . . . . . . . . . . . 95 N/A QFN (Note 4) . . . . . . . . . . . . . . . . . . . . 49 7 Max Power Dissipation at 25C in Free Air (SOIC, Note 3). 1.316W Max Power Dissipation at 25C in Free Air (QFN, Note 4) . .2.976W Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Maximum Junction Temperature Range . . . . . . . . .-40C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . +300C (SOIC - Lead Tips Only) For Recommended soldering conditions see Tech Brief TB389.
Maximum Recommended Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9V to 15V Voltage on HS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 75V Voltage on HS (Note 2) . . . . . . . . . .(Repetitive Transient) -1V to 80V Voltage on HB . . . . . . . . . . . . . . . . . . . . . . . . . . VHS +7.5V to VHS +VDD
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the recommended operating conditions of this specification is not implied.
NOTES: 1. All voltages referenced to VSS unless otherwise specified. 2. Based on VDD=15V. The magnitude of the allowable negative transient on the HS pin is a function of the VDD supply voltage. VHS<15.6VVDD+VF, where VHS is the magnitude of the allowable negative transient and VF is the forward voltage drop of the bootstrap diode. 3. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "direct attach" features. JC, the "case temp" is measured at the center of the exposed metal pad on the package underside. See Tech Brief TB379.
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified TJ = 25C TJ = -40C TO 125C MAX MIN MAX UNITS
PARAMETERS
SYMBOL
TEST CONDITIONS
MIN
TYP
SUPPLY CURRENTS & UNDERVOLTAGE PROTECTION VDD Quiescent Current VDD Operating Current VDD Operating Current HB Off Quiescent Current HB On Quiescent Current HB Operating Current HB Operating Current HS Leakage Current VDD Rising Undervoltage Threshold VDD Falling Undervoltage Threshold Undervoltage Hysteresis HB Undervoltage Threshold INPUT PINS: LI and HI Low Level Input Voltage High Level Input Voltage Input Voltage Hysteresis Low Level Input Current High Level Input Current IIL IIH VIN = 0V, Full Operating Conditions VIN = 5V, Full Operating Conditions VIL VIH Full Operating Conditions Full Operating Conditions 0.8 -70 30 1.6 1.7 100 -60 115 2.2 -30 130 0.8 -80 30 2.2 -30 145 V V mV A A IDD IDDO IDDO IHBL IHBH IHBO IHBO IHLK VDDUV+ VDDUVUVHYS VHBUV Referenced to HS LI = 0 or VDD f = 50kHz f = 500kHz HI = 0 HI = VDD f = 50kHz, CL = 1000pF f = 500kHz, CL = 1000pF VHS = 80V VHB = 96V 6.8 6.5 0.17 4.8 1.9 2.0 2.5 1.25 170 1.45 2.4 7.6 7.1 0.45 5.3 2.2 2.2 3.0 1.5 240 1.8 2.8 1 8.25 7.8 0.75 6.5 6.5 6.25 0.15 4.0 2.4 2.5 4.0 1.8 250 2.0 3.0 1 8.5 8.1 0.90 7.5 mA mA mA mA A mA mA A V V V V
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FN9077.6 December 29, 2004
ISL6700
Electrical Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified (Continued) TJ = 25C PARAMETERS GATE DRIVER OUTPUT PINS: LO & HO Low Level Output Voltage High Level Output Voltage Peak Pullup Current Peak Pulldown Current VOL VDD-VOH IO+ IO IOUT = 0A IOUT = 0A VOUT = 0V VOUT = 12V 1.4 1.3 0.1 0.1 0.1 0.1 V V A A SYMBOL TEST CONDITIONS MIN TYP MAX TJ = -40C TO 125C MIN MAX UNITS
Switching Specifications
VDD = VHB = 12V, VSS = VHS = 0V, No Load on LO or HO, Unless Otherwise Specified TJ = 25C MIN LI, HI switched simultaneously 0 0 TYP 45 60 75 70 24 17 5 5 8 -15 MAX 50 75 82 75 20 20 20 25 TJ = -40C TO 125C MIN 0 0 MAX 65 90 95 95 25 25 25 30 UNITS ns ns ns ns ns ns ns ns ns ns
PARAMETERS Lower Turn-off Propagation Delay (LI Falling to LO Falling) Upper Turn-off Propagation Delay (HI Falling to HO Falling) Lower Turn-on Propagation Delay (LI Rising to LO Rising) Upper Turn-on Propagation Delay (HI Rising to HO Rising) Deadtime, (tHPLH - tLPHL) Deadtime, (tLPLH - tHPHL) Rise Time Fall Time Delay Matching: Lower Turn-On and Upper Turn-Off Delay Matching: Lower Turn-Off and Upper Turn-On
SYMBOL tLPHL tHPHL tLPLH tHPLH DHtON DLtON tR tF tMON tMOFF
TEST CONDITIONS
Pin Descriptions
SYMBOL VDD HI LI VSS LO HS HO HB EPAD DESCRIPTION Positive supply to control logic and lower gate drivers. De-couple this pin to VSS. Connect anode of bootstrap diode to this pin. Logic level input that controls the HO output. Logic level input that controls the LO output. Chip negative supply, generally will be ground. Low-side output. Connect to gate of low-side power MOSFET. High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. High-side output. Connect to gate of high-side power MOSFET. High-side bootstrap supply. External bootstrap diode and capacitor are required. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to this pin. Exposed pad. Connect to ground or float. The EPAD is electrically isolated from all other pins.
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FN9077.6 December 29, 2004
ISL6700 Timing Diagrams
LI
HI, LI tHPLH , tLPLH HO, LO tHPHL, tLPHL
HI
LO tMON HO tMOFF
FIGURE 3.
FIGURE 4.
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FN9077.6 December 29, 2004
ISL6700 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L12.4x4
12 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L L1 N Nd Ne P 0.25 0.35 1.95 1.95 0.23 MIN 0.80 NOMINAL 0.90 0.20 REF 0.28 4.00 BSC 3.75 BSC 2.10 4.00 BSC 3.75 BSC 2.10 0.80 BSC 0.60 12 3 3 0.60 12 0.75 0.15 2.25 2.25 0.38 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 10 2 3 3 9 9 Rev. 1 5/03 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm.
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FN9077.6 December 29, 2004
ISL6700 Small Outline Plastic Packages (SOIC)
N INDEX AREA H E -B1 2 3 SEATING PLANE -AD -CA h x 45o 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 5.80 0.25 0.40 8 0o MAX 1.75 0.25 0.51 0.25 5.00 4.00 6.20 0.50 1.27 8o NOTES 9 3 4 5 6 7 Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497 0.2284 0.0099 0.016 8 0o
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574 0.2440 0.0196 0.050 8o
A1 B C D E e
C
A1 0.10(0.004)
e
B 0.25(0.010) M C AM BS
0.050 BSC
1.27 BSC
H h L N
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 8
FN9077.6 December 29, 2004

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